A digital-to-analog converter (“DAC”) is a device that generates an analog signal from an inputted digital signal. The DAC can be used in a variety of applications including data communications (including voice, video, etc.), measurement and testing devices, and data telemetry devices. Analog signals are continuous time-domain signals with infinite resolution. However, the DAC's output is a signal constructed from discrete values (or quantization) generated at uniform, but finite, time intervals (referred to as sampling). In other words, the DAC output attempts to represent an analog signal with one that features finite resolution and bandwidth.
Quantization and sampling impose fundamental limits on DAC performance. Quantization determines the maximum dynamic range of the converter and results in quantization error or noise in the output. Sampling determines the maximum bandwidth of the DAC output signal according to Nyquist criteria. The DAC operation is affected by non-ideal effects beyond those dictated by quantization and sampling. These errors are characterized by a number of performance specifications that determine the converter's static and dynamic performance.
In particular for a switched capacitor DAC, a non-ideal switch can lead to voltage drift of a bottom plate of a quantization cap of a switched capacitor DAC. In order to combat the voltage drift, a return-to-zero (“RZ”) scheme was implemented having a reset operation to occupy some of the conversion time to reset the digital output to a common mode voltage Vcm after each sampling. However, this doubles the transition numbers, limiting the max operation of the switched capacitor in an RZ scheme compared to a non-RZ (“NRZ”) scheme for a DAC.
FIG. 1a illustrates a non-return-to-zero impulse response for a switched capacitor DAC. The impulse response of a NRZ scheme shows that an envelope of the sampled digital input code is taken for an entire sampling cycle Ts. FIG. 1b illustrates a return-to-zero impulse response for a switched capacitor DAC. The impulse response of a RZ scheme shows that the envelope of the sampled digital input code only takes a part of the sampling cycle Ts since part of the sampling cycle is needed for the return to zero portion. Thereby, the RZ scheme is not as efficient as the NRZ scheme.
Although the RZ scheme is effective in preventing deviation of the DAC from the common mode voltage, it is desirable to provide new methods, apparatuses, and systems for preventing the deviation from the common mode voltage while minimizing the effect on the conversion time of the DAC.